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0110000 /*
0110001 dp8390.h
0110002
0110003 Created: before Dec 28, 1992 by Philip Homburg
0110004 */
0110005
0110006 /* National Semiconductor DP8390 Network Interface Controller. */
0110007
0110008 /* Page 0, for reading ------------- */
0110009 #define DP_CR 0x0 /* Read side of Command Register */
0110010 #define DP_CLDA0 0x1 /* Current Local Dma Address 0 */
0110011 #define DP_CLDA1 0x2 /* Current Local Dma Address 1 */
0110012 #define DP_BNRY 0x3 /* Boundary Pointer */
0110013 #define DP_TSR 0x4 /* Transmit Status Register */
0110014 #define DP_NCR 0x5 /* Number of Collisions Register */
0110015 #define DP_FIFO 0x6 /* Fifo ?? */
0110016 #define DP_ISR 0x7 /* Interrupt Status Register */
0110017 #define DP_CRDA0 0x8 /* Current Remote Dma Address 0 */
0110018 #define DP_CRDA1 0x9 /* Current Remote Dma Address 1 */
0110019 #define DP_DUM1 0xA /* unused */
0110020 #define DP_DUM2 0xB /* unused */
0110021 #define DP_RSR 0xC /* Receive Status Register */
0110022 #define DP_CNTR0 0xD /* Tally Counter 0 */
0110023 #define DP_CNTR1 0xE /* Tally Counter 1 */
0110024 #define DP_CNTR2 0xF /* Tally Counter 2 */
0110025
0110026 /* Page 0, for writing ------------- */
0110027 #define DP_CR 0x0 /* Write side of Command Register */
0110028 #define DP_PSTART 0x1 /* Page Start Register */
0110029 #define DP_PSTOP 0x2 /* Page Stop Register */
0110030 #define DP_BNRY 0x3 /* Boundary Pointer */
0110031 #define DP_TPSR 0x4 /* Transmit Page Start Register */
0110032 #define DP_TBCR0 0x5 /* Transmit Byte Count Register 0 */
0110033 #define DP_TBCR1 0x6 /* Transmit Byte Count Register 1 */
0110034 #define DP_ISR 0x7 /* Interrupt Status Register */
0110035 #define DP_RSAR0 0x8 /* Remote Start Address Register 0 */
0110036 #define DP_RSAR1 0x9 /* Remote Start Address Register 1 */
0110037 #define DP_RBCR0 0xA /* Remote Byte Count Register 0 */
0110038 #define DP_RBCR1 0xB /* Remote Byte Count Register 1 */
0110039 #define DP_RCR 0xC /* Receive Configuration Register */
0110040 #define DP_TCR 0xD /* Transmit Configuration Register */
0110041 #define DP_DCR 0xE /* Data Configuration Register */
0110042 #define DP_IMR 0xF /* Interrupt Mask Register */
0110043
0110044 /* Page 1, read/write -------------- */
0110045 #define DP_CR 0x0 /* Command Register */
0110046 #define DP_PAR0 0x1 /* Physical Address Register 0 */
0110047 #define DP_PAR1 0x2 /* Physical Address Register 1 */
0110048 #define DP_PAR2 0x3 /* Physical Address Register 2 */
0110049 #define DP_PAR3 0x4 /* Physical Address Register 3 */
0110050 #define DP_PAR4 0x5 /* Physical Address Register 4 */
0110051 #define DP_PAR5 0x6 /* Physical Address Register 5 */
0110052 #define DP_CURR 0x7 /* Current Page Register */
0110053 #define DP_MAR0 0x8 /* Multicast Address Register 0 */
0110054 #define DP_MAR1 0x9 /* Multicast Address Register 1 */
0110055 #define DP_MAR2 0xA /* Multicast Address Register 2 */
0110056 #define DP_MAR3 0xB /* Multicast Address Register 3 */
0110057 #define DP_MAR4 0xC /* Multicast Address Register 4 */
0110058 #define DP_MAR5 0xD /* Multicast Address Register 5 */
0110059 #define DP_MAR6 0xE /* Multicast Address Register 6 */
0110060 #define DP_MAR7 0xF /* Multicast Address Register 7 */
0110061
0110062 /* Bits in dp_cr */
0110063 #define CR_STP 0x01 /* Stop: software reset */
0110064 #define CR_STA 0x02 /* Start: activate NIC */
0110065 #define CR_TXP 0x04 /* Transmit Packet */
0110066 #define CR_DMA 0x38 /* Mask for DMA control */
0110067 #define CR_DM_NOP 0x00 /* DMA: No Operation */
0110068 #define CR_DM_RR 0x08 /* DMA: Remote Read */
0110069 #define CR_DM_RW 0x10 /* DMA: Remote Write */
0110070 #define CR_DM_SP 0x18 /* DMA: Send Packet */
0110071 #define CR_DM_ABORT 0x20 /* DMA: Abort Remote DMA Operation */
0110072 #define CR_PS 0xC0 /* Mask for Page Select */
0110073 #define CR_PS_P0 0x00 /* Register Page 0 */
0110074 #define CR_PS_P1 0x40 /* Register Page 1 */
0110075 #define CR_PS_P2 0x80 /* Register Page 2 */
0110076 #define CR_PS_T1 0xC0 /* Test Mode Register Map */
0110077
0110078 /* Bits in dp_isr */
0110079 #define ISR_MASK 0x3F
0110080 #define ISR_PRX 0x01 /* Packet Received with no errors */
0110081 #define ISR_PTX 0x02 /* Packet Transmitted with no errors */
0110082 #define ISR_RXE 0x04 /* Receive Error */
0110083 #define ISR_TXE 0x08 /* Transmit Error */
0110084 #define ISR_OVW 0x10 /* Overwrite Warning */
0110085 #define ISR_CNT 0x20 /* Counter Overflow */
0110086 #define ISR_RDC 0x40 /* Remote DMA Complete */
0110087 #define ISR_RST 0x80 /* Reset Status */
0110088
0110089 /* Bits in dp_imr */
0110090 #define IMR_PRXE 0x01 /* Packet Received iEnable */
0110091 #define IMR_PTXE 0x02 /* Packet Transmitted iEnable */
0110092 #define IMR_RXEE 0x04 /* Receive Error iEnable */
0110093 #define IMR_TXEE 0x08 /* Transmit Error iEnable */
0110094 #define IMR_OVWE 0x10 /* Overwrite Warning iEnable */
0110095 #define IMR_CNTE 0x20 /* Counter Overflow iEnable */
0110096 #define IMR_RDCE 0x40 /* DMA Complete iEnable */
0110097
0110098 /* Bits in dp_dcr */
0110099 #define DCR_WTS 0x01 /* Word Transfer Select */
0110100 #define DCR_BYTEWIDE 0x00 /* WTS: byte wide transfers */
0110101 #define DCR_WORDWIDE 0x01 /* WTS: word wide transfers */
0110102 #define DCR_BOS 0x02 /* Byte Order Select */
0110103 #define DCR_LTLENDIAN 0x00 /* BOS: Little Endian */
0110104 #define DCR_BIGENDIAN 0x02 /* BOS: Big Endian */
0110105 #define DCR_LAS 0x04 /* Long Address Select */
0110106 #define DCR_BMS 0x08 /* Burst Mode Select */
0110107 #define DCR_AR 0x10 /* Autoinitialize Remote */
0110108 #define DCR_FTS 0x60 /* Fifo Threshold Select */
0110109 #define DCR_2BYTES 0x00 /* 2 bytes */
0110110 #define DCR_4BYTES 0x40 /* 4 bytes */
0110111 #define DCR_8BYTES 0x20 /* 8 bytes */
0110112 #define DCR_12BYTES 0x60 /* 12 bytes */
0110113
0110114 /* Bits in dp_tcr */
0110115 #define TCR_CRC 0x01 /* Inhibit CRC */
0110116 #define TCR_ELC 0x06 /* Encoded Loopback Control */
0110117 #define TCR_NORMAL 0x00 /* ELC: Normal Operation */
0110118 #define TCR_INTERNAL 0x02 /* ELC: Internal Loopback */
0110119 #define TCR_0EXTERNAL 0x04 /* ELC: External Loopback LPBK=0 */
0110120 #define TCR_1EXTERNAL 0x06 /* ELC: External Loopback LPBK=1 */
0110121 #define TCR_ATD 0x08 /* Auto Transmit */
0110122 #define TCR_OFST 0x10 /* Collision Offset Enable (be nice) */
0110123
0110124 /* Bits in dp_tsr */
0110125 #define TSR_PTX 0x01 /* Packet Transmitted (without error)*/
0110126 #define TSR_DFR 0x02 /* Transmit Deferred */
0110127 #define TSR_COL 0x04 /* Transmit Collided */
0110128 #define TSR_ABT 0x08 /* Transmit Aborted */
0110129 #define TSR_CRS 0x10 /* Carrier Sense Lost */
0110130 #define TSR_FU 0x20 /* FIFO Underrun */
0110131 #define TSR_CDH 0x40 /* CD Heartbeat */
0110132 #define TSR_OWC 0x80 /* Out of Window Collision */
0110133
0110134 /* Bits in tp_rcr */
0110135 #define RCR_SEP 0x01 /* Save Errored Packets */
0110136 #define RCR_AR 0x02 /* Accept Runt Packets */
0110137 #define RCR_AB 0x04 /* Accept Broadcast */
0110138 #define RCR_AM 0x08 /* Accept Multicast */
0110139 #define RCR_PRO 0x10 /* Physical Promiscuous */
0110140 #define RCR_MON 0x20 /* Monitor Mode */
0110141
0110142 /* Bits in dp_rsr */
0110143 #define RSR_PRX 0x01 /* Packet Received Intact */
0110144 #define RSR_CRC 0x02 /* CRC Error */
0110145 #define RSR_FAE 0x04 /* Frame Alignment Error */
0110146 #define RSR_FO 0x08 /* FIFO Overrun */
0110147 #define RSR_MPA 0x10 /* Missed Packet */
0110148 #define RSR_PHY 0x20 /* Multicast Address Match !! */
0110149 #define RSR_DIS 0x40 /* Receiver Disabled */
0110150
0110151
0110152 typedef struct dp_rcvhdr
0110153 {
0110154 u8_t dr_status; /* Copy of rsr */
0110155 u8_t dr_next; /* Pointer to next packet */
0110156 u8_t dr_rbcl; /* Receive Byte Count Low */
0110157 u8_t dr_rbch; /* Receive Byte Count High */
0110158 } dp_rcvhdr_t;
0110159
0110160 #define DP_PAGESIZE 256
0110161
0110162 /* Some macros to simplify accessing the dp8390 */
0110163 #define inb_reg0(dep, reg) (in_byte(dep->de_dp8390_port+reg))
0110164 #define outb_reg0(dep, reg, data) (out_byte(dep->de_dp8390_port+reg, data))
0110165 #define inb_reg1(dep, reg) (in_byte (dep->de_dp8390_port+reg))
0110166 #define outb_reg1(dep, reg, data) (out_byte(dep->de_dp8390_port+reg, data))
0110167
0110168 /* Software interface to the dp8390 driver */
0110169
0110170 struct dpeth;
0110171 struct iovec_dat;
0110172 _PROTOTYPE( typedef void (*dp_initf_t), (struct dpeth *dep) );
0110173 _PROTOTYPE( typedef void (*dp_stopf_t), (struct dpeth *dep) );
0110174 _PROTOTYPE( typedef void (*dp_user2nicf_t), (struct dpeth *dep,
0110175 struct iovec_dat *iovp, vir_bytes offset,
0110176 int nic_addr, vir_bytes count) );
0110177 _PROTOTYPE( typedef void (*dp_nic2userf_t), (struct dpeth *dep,
0110178 int nic_addr, struct iovec_dat *iovp,
0110179 vir_bytes offset, vir_bytes count) );
0110180 #if 0
0110181 _PROTOTYPE( typedef void (*dp_getheaderf_t), (struct dpeth *dep,
0110182 int page, struct dp_rcvhdr *h, u16_t *eth_type) );
0110183 #endif
0110184 _PROTOTYPE( typedef void (*dp_getblock_t), (struct dpeth *dep,
0110185 int page, size_t offset, size_t size, void *dst) );
0110186
0110187 /* iovectors are handled IOVEC_NR entries at a time. */
0110188 #define IOVEC_NR 16
0110189
0110190 typedef struct iovec_dat
0110191 {
0110192 iovec_t iod_iovec[IOVEC_NR];
0110193 int iod_iovec_s;
0110194 int iod_proc_nr;
0110195 vir_bytes iod_iovec_addr;
0110196 } iovec_dat_t;
0110197
0110198 #define SENDQ_NR 2 /* Maximum size of the send queue */
0110199 #define SENDQ_PAGES 6 /* 6 * DP_PAGESIZE >= 1514 bytes */
0110200
0110201 typedef struct dpeth
0110202 {
0110203 /* The de_base_port field is the starting point of the probe.
0110204 * The conf routine also fills de_linmem and de_irq. If the probe
0110205 * routine knows the irq and/or memory address because they are
0110206 * hardwired in the board, the probe should modify these fields.
0110207 * Futhermore, the probe routine should also fill in de_initf and
0110208 * de_stopf fields with the appropriate function pointers and set
0110209 * de_prog_IO iff programmed I/O is to be used.
0110210 */
0110211 port_t de_base_port;
0110212 phys_bytes de_linmem;
0110213 int de_irq;
0110214 dp_initf_t de_initf;
0110215 dp_stopf_t de_stopf;
0110216 int de_prog_IO;
0110217 char de_name[sizeof("dp8390#n")];
0110218
0110219 /* The initf function fills the following fields. Only cards that do
0110220 * programmed I/O fill in the de_pata_port field.
0110221 * In addition, the init routine has to fill in the sendq data
0110222 * structures.
0110223 */
0110224 ether_addr_t de_address;
0110225 port_t de_dp8390_port;
0110226 port_t de_data_port;
0110227 int de_16bit;
0110228 int de_ramsize;
0110229 int de_offset_page;
0110230 int de_startpage;
0110231 int de_stoppage;
0110232
0110233 /* Do it yourself send queue */
0110234 struct sendq
0110235 {
0110236 int sq_filled; /* this buffer contains a packet */
0110237 int sq_size; /* with this size */
0110238 int sq_sendpage; /* starting page of the buffer */
0110239 } de_sendq[SENDQ_NR];
0110240 int de_sendq_nr;
0110241 int de_sendq_head; /* Enqueue at the head */
0110242 int de_sendq_tail; /* Dequeue at the tail */
0110243
0110244 /* Shared memory segment and offset based on de_linmem. */
0110245 u16_t de_memseg;
0110246 vir_bytes de_memoff;
0110247
0110248 /* Fields for internal use by the dp8390 driver. */
0110249 int de_flags;
0110250 int de_mode;
0110251 eth_stat_t de_stat;
0110252 iovec_dat_t de_read_iovec;
0110253 iovec_dat_t de_write_iovec;
0110254 iovec_dat_t de_tmp_iovec;
0110255 vir_bytes de_read_s;
0110256 int de_client;
0110257 message de_sendmsg;
0110258 dp_user2nicf_t de_user2nicf;
0110259 dp_nic2userf_t de_nic2userf;
0110260 dp_getblock_t de_getblockf;
0110261 } dpeth_t;
0110262
0110263 #define DEI_DEFAULT 0x8000
0110264
0110265 #define DEF_EMPTY 0x000
0110266 #define DEF_PACK_SEND 0x001
0110267 #define DEF_PACK_RECV 0x002
0110268 #define DEF_SEND_AVAIL 0x004
0110269 #define DEF_READING 0x010
0110270 #define DEF_PROMISC 0x040
0110271 #define DEF_MULTI 0x080
0110272 #define DEF_BROAD 0x100
0110273 #define DEF_ENABLED 0x200
0110274 #define DEF_STOPPED 0x400
0110275
0110276 #define DEM_DISABLED 0x0
0110277 #define DEM_SINK 0x1
0110278 #define DEM_ENABLED 0x2
0110279
0110280 #if !__minix_vmd
0110281 #define debug 0 /* Standard Minix lacks debug variable */
0110282 #endif
0110283
0110284 /*
0110285 * $PchId: dp8390.h,v 1.5 1995/12/22 08:53:00 philip Exp $
0110286 */